Quick Heal Total Security 2009 +Crack

Quick Heal Total Security 2009 gives you complete protection from viruses, spywares, and hackers. It also helps you stay connected and communicate over the internet by preventing your system from threats over the Internet. With Quick Heal Total Security in your PC--Enjoy your freedom to work and play in the connected world. With Quick Heal Total Security 2009 in your PC, you can scan and clean mobile phone connected via Bluetooth or USB cable.

Version 10.0 adds a new advanced malware scanning engine that scans registry, files and folders at lightening speed to thoroughly detect and clean Spywares, Adwares, Roguewares, Dialers, Riskwares and lots of other potential threats in your system.

DOWNLOAD TORRENT

Kaspersky Internet Security 2010-9.0.0.736, Free Torrent Download

Kaspersky Internet Security 2010 automatically protects you and your family at all times whether you work, bank, shop or play online. Kaspersky Internet Security 2010 has everything you need for a safe and secure Internet experience. All the features and technologies of Kaspersky Anti-Virus 2010 are included in this product.

DOWNLOAD TORRENT 

Instructions:                    

1)Disconnect From The Internet.
2)Click On License (At The Bottom Of Kapsersky Main Window).
   A New window Called "License manager" Will Open.
    If A Key Already Exist Click On The 'X' Button Infront Of It And Press      Yes To Delete The Key]
3)Click On "Activate New License".
    A New Window Called "Kaspersky Internet Security Activation Wizard" Will Open.
4)Click On "Activate Trial License".
5)Press Next.
6)Press OK.
7)In "Key File" Click "Browse" And Search For The Key.
   Choose A Key And Click Next.
8)Enjoy!!

ASIC Implementation Design Cycle

Ubuntu giving problem when installed in Thumb Drive

Hi friends, I had faces a strange situation couple of days before, i am having XP operating system in my Laptop and I tried to install Ubuntu in my thumb drive, after being done with the task i found a strange problem. My PC needs thumb drive plugged in every time when i want to boot it. That was quite irritating, and if suppose any problem comes then your pc will not get booted and at last you need to upgrade your OS and that's the think i don't like to do.

I searched a lot in the web and found a simple solution of it. The Thing that had happened was quite obvious, as i installed Ubuntu after my Xp, Ubuntu now had moved MBR (Memory Boot Record) to the thumb drive and that was creating all the problem. at the booting process laptop was always searching the MBR in thumb drive and when i kept thumb drive unplugged it was showing error. the thing i had to do was to set the MBR of Windows XP.

This can be done very easily, you just need to boot your pc with Windows Xp CD and after going into recovery console type the following command:

fixmbr

this will surely help you out with your problem.

get more information about MBR from Here

What is a Trojan horse program?

A type of program that is often confused with viruses is a 'Trojan horse'
program.  This is not a virus, but simply a program (often harmful) that 
pretends to be something else.

Clam AntiVirus

Clam AntiVirus is an open source (GPL) anti-virus toolkit for UNIX, designed especially for e-mail scanning on mail gateways. It provides a number of utilities including a flexible and scalable multi-threaded daemon, a command line scanner and advanced tool for automatic database updates. The core of the package is an anti-virus engine available in a form of shared library.

Here is a list of the main features:

• command-line scanner
• fast, multi-threaded daemon with support for on-access scanning
• milter interface for sendmail
• advanced database updater with support for scripted updates and digital signatures
• virus scanner C library
• on-access scanning (Linux® and FreeBSD®)
• virus database updated multiple times per day (see home page for total number of signatures)
• built-in support for various archive formats, including Zip, RAR, Tar, Gzip, Bzip2, OLE2, Cabinet, CHM, BinHex, SIS and others
• built-in support for almost all mail file formats
• built-in support for ELF executables and Portable Executable files compressed with UPX, FSG, Petite, NsPack, wwpack32, MEW, Upack and obfuscated with SUE, Y0da Cryptor and others
• built-in support for popular document formats including MS Office and MacOffice files, HTML, RTF and PDF

McAfee Virus Scan Enterprise 8.7i

McAfee is pleased to
announce the Release Candidate (RC) for VirusScan Enterprise 8.7i and
AntiSpyware Enterprise Module 8.7.
This release of VirusScan
Enterprise 8.7i contains defect fixes, incorporates the Beta 2 release of the
5300 scanning engine, and a number of features that improve performance of
malware scanning and incorporates functional and usability improvements. Providing
this new functionality required making architectural changes to the product
infrastructure. While we have performed extensive testing to ensure that these
changes don’t impact the overall stability of the product, we urge you to
download this beta version, test all features in environments that are similar
to your production environments, and provide us feedback to help us further
improve the stability and quality of the release.
Enhance your security with
real-time malware protection now available with VirusScan Enterprise 8.7i!
A new
feature, "Heuristic network check for suspicious files,"
provides customers with real-time detections for malware.
·        
This feature uses sensitivity levels that can be
configured based on your risk tolerance, to look for suspicious files on your
endpoints that are running VirusScan Enterprise 8.7i.
·        
When enabled, this feature detects a suspicious
program and sends a DNS request containing a fingerprint of the suspicious file
to McAfee Avert Labs which then communicates the appropriate action back to
VirusScan Enterprise 8.7i.
·        
 The real-time defense feature also provides
protection for classes of malware for which signatures might not be available.
·        
This protection is in addition to the world-class
DAT-based detection VirusScan Enterprise has always provided.  The user
experience remains the same and no additional client software is required.
·        
In this release, this optional feature is available only
for on-demand scans and email scanning and is disabled by default. You must
select a sensitivity level to enable the feature. We encourage you to try out
this feature and provide us valuable feedback so that we can continue to
enhance our industry leading malware protection capabilities. See the New Features
tab and the Product Guide for more details.
Please see New Product
Features below and the product release notes for additional details of product
changes.
>> McAfee VirusScan
Enterprise V8.7.0i (Multilanguage)



Note: This is NOT the Beta
or RC (Realize Candidate) Version.


Enjoy and Seed.

DOWNLOAD

HDL Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

Netgen - The Circuit Netlist Comparison (LVS) and Netlist Conversion Tool

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).

Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.

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IRSIM - tThe Switch-level Digital Circuit Simulator.

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

IRSIM shares a history with magic, although it is an independent program. Magic was designed to produce, and IRSIM to read, the ".sim" file format, which is largely unused outside of these two programs. IRSIM was developed at Stanford, while Magic was developed at Berkeley. Parts of Magic were developed especially for use with IRSIM, allowing IRSIM to run a simulation in the "background" (i.e., a forked process communicating through a pipe), while displaying information about the values of signals directly on the VLSI layout.

For "quick" simulations of digital circuits, IRSIM is still quite useful for confirming basic operation of digital circuit layouts. The addition of scheduling commands ("at", "every", "when", and "whenever") put IRSIM into the same class as Verilog simulators. It is, in my opinion, much easier to write complicated testbench simulations using Tcl and IRSIM. I have used IRSIM to validate the digital parts of several production chips at MultiGiG, including the simulation of analog behavior such as PLL locking.

IRSIM version 9.5 was a long-standing and stable version that corresponded to the relatively stable Magic version 6.5. When magic was recast in a Tcl/Tk interpreter framework (versions 7.2 and 7.3), IRSIM could no longer operate as a background process. However, it was clear that if IRSIM could also be recast in the same Tcl/Tk interpreter framework, the level of interaction between it and Magic would be greatly increased.

I set about to create the "new" IRSIM, although it came along in fits and starts as I had time to work on it. Because the original "analyzer" graphic display window (and GUI, to a very limited extent) was written in Xt (the rather primitive window system that is an integral part of X11), it was scrapped for a while. In its place, I substituted graphs in "Blt" based on the same in "tclspice" (see SourceForge for the tclspice project). Unfortunately, "Blt" insists that all data vectors must be real-valued, which is 1) a severe waste of space for binary digital values, and 2) is unable to represent the concept of an "unknown" value that is so crucial to fast switch simulation. So, eventually I was forced to scrap BLT and actually sit down and code out a real Tcl-based analyzer window and GUI. The result is finally done in revision 9.7.3.

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XCircuit - The Circuit Drawing and Schematic Capture Tool

There are drawing programs, and there are schematic capture programs. All schematic capture programs will produce output for inclusion in publications. However, these programs have different goals, and it shows. Rarely is the output of a schematic capture program really suitable for publication; often it is not even readable, or cannot be scaled. Engineers who really want to have a useful schematic drawing of a circuit usually redraw the circuit in a general drawing program, which can be both tedious and prone to introducing new errors.

XCircuit is a UNIX/X11 (and Windows, if you have an X-Server running, or Windows API, if not) program for drawing publishable-quality electrical circuit schematic diagrams and related figures, and produce circuit netlists through schematic capture. XCircuit regards circuits as inherently hierarchical, and writes both hierarchical PostScript output and hierarchical SPICE netlists. Circuit components are saved in and retrieved from libraries which are fully editable. XCircuit does not separate artistic expression from circuit drawing; it maintains flexiblity in style without compromising the power of schematic capture.

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Magic - The VLSI Layout Editor, Extraction, and DRC Tool.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

DOWNLOAD

Xilinx ISE Design suite 10.1

Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design environment that allows you to design Xilinx FPGA and CPLD devices from start to finish. ISE includes our world class design entry, synthesis and implementation tools delivering the industry's fastest place and route times, highest performance, and most advanced design methodologies.

Project Navigator is the user interface that helps you manage the entire design process including design entry, simulation, synthesis, implementation and finally download the configuration of your FPGA or CPLD device.

The following is an outline of the features offered in ISE.

Design Entry

• HDL Editor
• StateCAD State Machine Editor
• Schematic Editor - Engineering Capture System (ECS)
• CORE Generator

Synthesis

• XST - Xilinx Synthesis Technology
• Integration with LeonardoSpectrum from Mentor Graphics, Inc.
• Integration with Synplify from Synplicity, Inc.

Simulation

• HDL Bencher Testbench Generator
• Integration with ModelSim Simulator from Model Technology, Inc.

Implementation

• Translate
• MAP
• Place and Route (PAR)
• Floorplanner
• FPGA Editor
• Timing Analyzer
• XPower
• Fit (CPLD only)
• Chipviewer (CPLD only)

Device Download and Program File Formatting

• BitGen
• iMPACT

Download the Xilinx ISE 10.1 design suit from Here

VLSI Training In Ahmedabad, Gujarat

Chip design in India has been identified as a prominent industry to support the already achieved development in IT field. With growing design houses day by day, a large pool of highly skilled individuals is needed to meet this demand. But, a potential gap was evident in the expectations of the industry and the output from academic institutions.

Realizing this need for trained manpower, we had launched a Certificate in Digital VLSI Design with emphasis on Digital CMOS circuit design, VLSI design flows, verification and testing. This course will be effective in providing potential engineers with exposure to both front-end and back-end processes in VLSI Design.

At Xpert teach. Ahmedabad we are offering courses in VLSI Front-end designing with following course contents.

I. Advance digital design

Combinational Logic Design

Sequential Logic Design

Programmable Logic

State Machines

II. Designing with Hardware Description Language (HDL)

Digital designing using VHDL

Digital designing using Verilog

HDL sumulation Using Modelsim

HDL synthesis using Xilinx ISE

Timing Analysis

FPGA Architecture

Verification Of Designs

III. CMOS designing

IV. Application Specific Integrated Circuits (ASICs)

Highlights of VLSI training at Xpert teach. :

Advanced Digital Design And Verilog Coding Techniques

Advanced Verification Techniques

Synthesis and Static Timing Analysis

Floor Planning, Placement And Routing

Version Control Mechanisms and Tools

Interview Preparation and Mock Interviews

For more detail contact

VISHAL PATEL:

vlsiencyclopedia@gmail.com

AMD and Intel Announce Settlement of All Antitrust and IP Disputes

Intel Corporation and Advanced Micro Devices (NYSE: AMD) today announced a comprehensive agreement to end all outstanding legal disputes between the companies, including antitrust litigation and patent cross license disputes.

In a joint statement the two companies commented, "While the relationship between the two companies has been difficult in the past, this agreement ends the legal disputes and enables the companies to focus all of our efforts on product innovation and development."

Under terms of the agreement, AMD and Intel obtain patent rights from a new 5-year cross license agreement, Intel and AMD will give up any claims of breach from the previous license agreement, and Intel will pay AMD $1.25 billion. Intel has also agreed to abide by a set of business practice provisions. As a result, AMD will drop all pending litigation including the case in U.S. District Court in Delaware and two cases pending in Japan. AMD will also withdraw all of its regulatory complaints worldwide. The agreement will be made public in filings with the Securities and Exchange Commission.

http://www.amd.com/us/press-releases/Pages/amd-press-release-2009nov12.aspx

ELECTRIC VLSI Design Software

The Electric^TM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:

• Custom IC Layout
• Schematic Capture (Digital and Analog)
• Textual Languages such as VHDL and Verilog
• ....and much more.

The Electric VLSI Design System is a highly flexible and powerful system that can handle many different types of circuit design (MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc.) It handles geometry at any angle (not just Manhattan) and can even handle curves.

Layout is done by placing and wiring electrical components. Although this is standard practice for schematics, it is unusual for chip layout. However, because of this style of design, Electric understands chip layout at a more sophisticated level, and can aid in design to an unprecedented degree.

Electric has many analysis tools, including design-rule checking, simulation, and network comparison. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation.

The user interface is quite sophisticated and runs on all popular workstations (Windows, Macintosh, and UNIX). It also provides interpretive languages for advanced users.

The software is freely available at www.staticfreesoft.com

VLSI Interview Questions-1

1. what is the difference between mealy and moore state-machines
2. how to solve setup and hold violations in the design
3. what is antenna violation & ways to prevent it
4. we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
5. what is tie-high and tie-low cells and where it is used
6. what is the difference between latches and flip-flops based designs
7. what is High-Vt and Low Vt cells
8. what is LEF mean?
9. what is DEF mean?
10. steps involved in designing an optimal padring
11. what is metastability and steps to prevent it
12. what is local-skew, global skew and useful skew
13. what are the various timing-paths which i should take care in my STA runs?
14. what are the various components of leakage-power
15. what are the various yield losses in the design
16. what is meant by virtual clock definition and why do i need it
17. what are the various variations which impacts timing of the design
18. what are the various Design constraints used, while performing synthesis for a design
19. specify few verilog constructs which are not supported by the synthesis tool
20. what are the various capacitances with an MOSFET?
21. Vds-Ids curve for an MOSFET, with increasing Vgs
22. explain basic operation of an MOSFET
23. what is channel length modulation
24. what is body effect
25. what is latchup in CMOS design and ways to prevent it?
26. what are the various design changes you do to meet design power targets
27. what is meant by library characterization
28. what is meant by wireload model
29. what are the measures to be taken to design for optimized area
30. what all will you be thinking while performing floorplan
31. what are the measures in the design taken for meeting signal integrity targets
32. what are the measures taken in the Design achieving better yield
33. what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
34. what are the steps incorporated for Engineering Change order[ECO]
35. what are the steps performed to achieve Lithography friendly Design
36. what does synthesis mean?
37. what are the pre-requistes to perform synthesis
38. can you explain the synthesis flow
39. what are the various ways to reduce clock insertion delay in the design
40. what are the various functional verification methodologies
41. what does formal verification mean
42. how will you time the output path in STA
43. how will you time the input path in STA
44. what is false path mean in STA and in what scenarios falsepath can come
45. what does multicycle path mean in STA and in what scenarios MCP can come
46. what are source synchronous paths in STA
47. Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
48. we have multiple instances in RTL, do you do anything special during synthesis stage
49. what do you call an event and when do you call an assertion.
50. what is difference between FPGA and ASIC.

Solutions to these questions will be provided on request.

mail me at vlsi.vishal@gmail.com